Description
Job Description
You will be part of the 32-bit microcontroller business unit and more specifically of the SoC design team. This team oversees the design of 32-bit microcontroller SoC's from specification to stream-out.
As a part of the SoC Design Engineer, the mission is to prototype the whole IPs related to the System power Management (SPM) in FPGA.
Some of these IPs (interacting with the SPM core) are not already modelized in RTL and so they will have to be designed in SystemVerilog.
This FPGA is intended to validate the whole SPM behavior before the silicon.
Note regarding the SPM: the name given to all the digital IPs providing the following functions: reset controller, startup clock management, power supply controller including internal regulators controller, sleep mode management.
What's attractive about this opportunity?
This position will allow you to work in a rich technical environment, dealing with hardware RTL level (SystemVerilog) and FPGA tools (Xilinx platform based on Virtex FPGA using synplify synthesis tool).
For RTL level, one part of the internship would be to design new digital modules in System Verilog to mimic analog IPs interacting with the SPM digital IPs.
Basic tests and simulation are also required to verify the system, by using QuestaSim simulator. For that, basic tests coded in C for microcontroller target will have to be written.
More details on the expectations and responsibilities in this position:
Within the team, the candidate will contribute to:
- Develop digital IPs in system Verilog to mimic the basic behavior of analog cells interacting with the digital SPM IPs.
- These system Verilog IPs need to be synthesized on FPGA.
Virtex 7 or Ultrascale FPGA from Xilinx.
Proposes modifications on the SPM digital IPs to allow prototyping in FPGA. Basically, some adaptation would be likely to be necessary around clock and reset structures.
Verify the whole system in a test-bench environment based on C code program written for 32-bit microcontroller target (ARM).
These basic tests will run on the QuestaSim simulator.
Prototyping on FPGA by using the standard flow: synplify synthesis tool from Synopsys, Vivado Place&Route tool from Xilinx.
Board prototyping are VC707 or VCU108 from Xilinx.
Requirements / Qualifications:
Qualifications and Experience
- BSc or MSc or Engineer degree in Electronics Engineering.
Key:
- Team player, working well in a team structure
- Hardware Description Language (VERILOG or VHDL or SYSTEM VERILOG)
- Knowledge in FPGA prototyping and Synthesis tool.
- Knowledge in digital simulator tool (like QuestaSim for example).
- C code language.
- Ability to communicate and work with different cultures in different countries.
Languages required: French (fluent). Good communications skills in writing and speaking English.
Travel Time: No Travel